Design And Reuse

EdgeAI Licensed Andes Technology CPU IP to Power Next-Generation Edge AI Neuromorphic Solution

SEOUL, SOUTH KOREA and HSINCHU, TAIWAN – EdgeAI Inc. a pioneering South Korean AI semiconductor startup specializing in ultra-low-power neuromorphic hardware, and Andes Technology (TWSE: 6533), a ...
Design And Reuse

Sovereign European chips could become a RISC-V-based reality

A sovereign IT infrastructure is open to interpretation. Only the American hyperscalers consider data residency sufficient to call an IT stack sovereign. Rarely, however, is the physical hardware ...
Design And Reuse

Murata and Synopsys collaborate to streamline simulation workflows for electronics designers

Murata Manufacturing is collaborating with Synopsys to provide easier access to its component simulation models through widely used engineering analysis tools, aiming to simplify ...
Design And Reuse

DDR Verification Challenges in Modern Chip Design

That’s the reality of modern DDR verification. Double Data Rate (DDR) memory interfaces are fundamental to modern SoC and ASIC designs, enabling high-bandwidth communication between processors and ...
Design And Reuse

M31 talks about 12 FFC Multi-Port Register Array

A multi-port register file, simply refers to an array composed of multiple registers within a processor, also known as a multi-port register array. It is a common type of memory used in processors ...
Design And Reuse

Beyond Moore’s Law: Heterogeneous Computing and AI SoCs

Heterogeneous computing enables specialized processors to deliver greater performance and efficiency than general-purpose architectures alone. The winners of the AI era will be those that master data ...
Design And Reuse

TSMC (NYSE:TSM) Is Raising 7nm Chip Prices Up To 10% As Expansion Builds

TSMC is reported to be raising prices by 5% to 10% on 7nm and below chip manufacturing processes. The price changes target leading edge capacity used in AI, datacenter, and high performance computing ...
Design And Reuse

Advanced USB Connectivity IP Validated on N2P Process Technology

Taiwanese semiconductor IP provider M31 Technology has announced the successful tapeout of its eUSB2V2 interface IP on TSMC’s N2P process technology, marking a significant advancement in the ...
Design And Reuse

T2M’s Cellular IP Core Portfolio: Accelerate SoC Innovation with Faster Time-to-Market, Lower Risk, and Superior PPA.

Cat-1bis IP – 3GPP Rel-19 compliant solution with integrated protocol stack, optimized for low-power IoT, smart metering, asset tracking, and industrial automation. NTN IP – Comprehensive satellite ...
Design And Reuse

RISC-V Market Leadership Helped Andes Technology Drive Cumulative Shipments of AndesCore-Powered™ SoCs Beyond the 20 Billion Mark

Andes Technology Corporation (TWSE: 6533), a leading provider of high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier Member of RISC-V International, today announced a ...
Design And Reuse

Siemens recognized as a Visionary in Gartner Magic Quadrant for AI Platforms for Data Science and Machine Learning

Siemens announced today that it has been recognized as a Visionary in the current Gartner® Magic Quadrant™ for AI Platforms for Data Science and Machine Learning 2026 1 ­. Siemens’ AI fabric, ...
Design And Reuse

STMicroelectronics unveils world’s first ST54M secure mobile chip with post-quantum cryptography for next-generation connected services

STMicroelectronics (NYSE: STM), a global semiconductor leader serving customers across the spectrum of electronics applications, has introduced the ST54M, a secure mobile chip designed to help ...